Read only memories (ROMs) typically serve as a nonvolatile source of data storage. Volatile memory devices, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs) can store data, but once power is removed from such devices, the data is lost. In contrast, nonvolatile memory devices, such as ROMs, electrically programmable ROMs (EPROMs), and electrically erasable and programmable ROMs (EEPROMs) retain data in the absence of power. Because of this, nonvolatile storage devices can be particularly suited for portable battery powered applications where power conservation is at a premium.
Because semiconductor memory devices include arrays of very small memory cells, the data signals provided by such memory cells are correspondingly small, and require amplification. As a result, semiconductor memory devices employ "sense" amplifiers to amplify data signals. Sense amplifiers are typically differential amplifiers that receive a data signal at one input and a reference signal at another input. A common way to increase the sensitivity with which data signals can be detected, is to take advantage of the matching physical characteristics of adjacent memory cell arrays by utilizing a "balanced" sensing arrangement.
Referring now to FIGS. 1A and 1B, a prior art balanced sensing arrangement will be described. FIG. 1A and 1B illustrate different balanced access operations for the same memory device. The memory device is designated by the general reference character 100, and is shown to include an upper array 102 and a lower array 104. Both the upper and lower arrays (102 and 104) include memory cells that are accessed by way of word lines and bit lines. Selected bit lines are indicated in the figures by the reference character 106. When a word line is activated, it places data signals from a row of memory cells onto the bit lines of its corresponding array. An activated word line is indicated in each figure by the reference character 108.
The bit lines 106 from both arrays (102 and 104) are coupled to sense amplifiers 110 by multiplexer (MUX) circuits 112. The sense amplifiers 110 are arranged in a bank between the two arrays (102 and 104). In the particular arrangement of FIG. 1, a group of four bit lines 106 is connected by one of the MUX circuits 112 to one of the sense amplifiers 110. The sense amplifiers 110 are coupled to the MUX circuits 112 of the upper array by upper data lines 114, and to MUX circuits 112 of the lower array by lower data lines 116.
A balanced sensing arrangement is achieved by providing essentially matching impedances at the two inputs of the sense amplifiers 110. In FIGS. 1A and 1B this is accomplished by activating the MUX circuits 112 of both the upper and lower arrays (102 and 104) when either the upper or lower array (102 and 104) is accessed. This is illustrated by the two figures. In FIG. 1A, the activated word line 108 is in the upper array 102. As a result, data signals from the upper array 102 are coupled to a first input of each sense amplifier 110. This operation presents an impedance at each first sense amplifier input that includes an upper data line 114 and a bit line 106 of the upper array 102. A balanced impedance for the second input of each sense amplifier 110 is provided by simultaneously enabling the MUX circuits 112 of the lower array 104. This presents an impedance at the second input of each sense amplifier 110 that includes a lower data line 116 and a bit line 106 of the lower array 104. Because a word line within the lower array is not activated, data is not present on the lower data lines 116. Instead, a reference signal is placed on lower data lines 116. Provided the lower data lines 116 are the same as the upper data lines 114, and the bit lines 106 of the upper and lower arrays are identical, the inputs to the sense amplifiers 110 will have a matching impedance. This arrangement provides for higher common noise rejection, and hence a more sensitive data sensing scheme. The two bit lines are also simultaneously biased to a fixed voltage which also improves common mode sensing.
FIG. 1B is provided to illustrate that when the lower array 104 is accessed for data, the upper array 102 can provide a balancing impedance. In such an operation, the upper data lines 114 would be coupled to a reference signal.
Balanced sensing schemes, while effective in some semiconductor memory devices, can be problematic when applied to others. In particular, balanced sensing schemes in "flash" EEPROMs can lead to operational drawbacks. Flash EEPROMs derive their name from the manner in which they are erased. In a conventional EEPROM, selected memory cells are erased individually, or in limited numbers, such as bytes. Thus, the erasure of an entire conventional EEPROM can be a lengthy process. In contrast, a flash EEPROM allows the simultaneous erasure of a large group of memory cells (sometimes referred to as "blocks," "banks" or "sectors"). To better understand the drawbacks associated with implementing balanced sensing schemes in flash EEPROMs, the operation of a typical flash EEPROM cell will be discussed.
In the typical flash EEPROM cell, the data signal is a current signal. This arises out of the fact that the flash EEPROM memory cell employs a "floating" gate. The floating gate is disposed between a control gate and a channel region to alter the threshold voltage of the resulting insulated gate field effect transistor structure. If the memory cell is programmed, the floating gate is negatively charged, and when its respective transistor is accessed, the threshold voltage of the cell will be higher than the applied control gate voltage. The cell will draw no (or negligible) current, establishing a logic "0." If the memory cell is erased, the floating gate will possess only limited negative charge, and the application of the applied control gate voltage results in channel inversion within the cell. The cell will thus draw current when accessed, thereby establishing a logic "1."
The erasing of flash EEPROM cells can give rise to an undesirable memory cell state referred to as depletion or "over-erase." In such a state, the floating gate is essentially positively charged, and the memory cell functions like a depletion mode transistor. Consequently, a depleted flash EEPROM memory cell cannot be turned off with the standard control gate voltages. Fortunately, depleted flash EEPROM cells can be corrected by a soft program operation (also referred to as "repair," "heal," and "compaction"). The soft program injects a small amount of negative charge back into the floating gate, allowing the memory cell to function as an enhancement device once again. The erase process and occasional soft program process result in flash EEPROM erase operations being considerably longer than read operations.
If flash EEPROM memory cells could be maintained at all times in their established logic states (i.e., programmed or erased), the use of balanced sensing schemes within EEPROMs would not be so problematic. To illustrate this, an ideal balanced sensing EEPROM arrangement is set forth in FIG. 2A. FIG. 2A includes a sense amplifier 200 having a first input (+) and a second input (-). According to the difference in current seen at these two inputs, the sense amplifier 200 provides a DATA signal. The first input (+) is shown to be coupled to an tipper data line 202, a MUX circuit 204, and an upper array bit line 206. Two memory cells (Q200 and Q202) are shown coupled to the upper array bit line 206. The second input (-) is balanced with the first input (+), and is shown to be coupled to a lower data line 208, a MUX circuit 204, and a lower array bit line 210. Two memory cells (Q204 and Q206) are shown coupled to the tipper array bit line 206. The memory cells (Q200, Q202, Q204, and Q206) of FIG. 2A are "one transistor" (1-T) EEPROM cells.
In the particular access illustrated by FIG. 2A, it is assumed that data is read from memory cell Q202, and further, that memory cell Q202 is erased. Thus, when a high voltage is applied to the gate of memory cell Q202 (by an active word line), a current will be drawn by the memory cell (shown as Idata). At the same time, a reference current source 212 is coupled to the second input (-) of the sense amplifier. In the ideal situation, the Idata current is greater than the Iref current, and the sense amplifier 200 provides a logic "1" as an output.
FIG. 2B illustrates the same structure and access operation as FIG. 2A, but includes the non-ideal effects that arise from the presence of depleted memory cells. Accordingly, the circuit structures of FIG. 2B are referred to by the same reference characters as those in FIG. 2A. In the access operation illustrated by FIG. 2B, it is assumed that prior to the reading of data from memory cell Q202, the memory cells of the lower array (Q204 and Q206) have been subject to an erase operation. The erase operation has resulted in memory cell Q204 being placed in the depleted state. Prior to the necessary soft program operation, which would have corrected memory cell Q204, the erase operation was suspended to allow the reading of memory cell Q202 to take place.
As shown in FIG. 2B, like the access illustrated by FIG. 2A, memory cell Q2 12 is erased, and so draws a current Idata. Similarly, the reference current source 212 has been coupled to the second input (-) of the sense amplifier, resulting in the current Iref being drawn at the second input (-). However, unlike the ideal case of FIG. 2A, in FIG. 2B depleted memory cell Q204 also draws a current of its own (Idep), despite the fact that its control gate is low. Consequently, the second input (-) draws a current equal to Iref+Idep, as opposed to Iref only. This can result in the data sense operation taking too much time, or in a worst case situation, an erroneous DATA signal altogether.
In light of the potential problem presented by depleted memory cells, balanced sensing arrangements are not possible when the array providing the balanced load is being erased. This has resulted in flash EEPROMs that do not employ balanced sensing at all, and suffering in performance as a result, or flash EEPROMs that do not allow a read operation from one array while its corresponding "balancing" array is being erased. The latter approach can lead to unacceptably long read cycles as erase operations can consume considerable time.
It would be desirable to provide an EEPROM that allows balanced sensing while one of the arrays is being erased. Such an EEPROM could provide considerably more operational flexibility as well as improved speed, and data sensing performance.